About

Mamta Rana is a highly skilled Senior Principal Product Engineer with over 10 years of experience in VIP/IP development and verification using SV-UVM and OVM methodologies. Currently working at Cadence Design Systems, she has a strong background in the standard PCIe protocol. Mamta has worked with leading companies in the industry, including stmicroelectronics and truechip solutions. At stmicroelectronics, she was responsible for developing a verification environment in SV using UVM for single port memory models. She also developed verification components agents, monitors, and drivers using SV-UVM methodology. At truechip solutions, Mamta worked on the AMBA AXI4 Stream, a bus-based high-speed communication interface and an interconnect protocol optimized for high bandwidth and reliable packet transfer. She was responsible for creating test plans, directed and random test sequences, and functional coverage using SV-UVM. Mamta holds a degree in Software Engineering and has been in the industry for over 12.70 years. Her technical stack includes skills in software engineering and testing. Mamta is a highly motivated individual with a passion for technology and a strong work ethic. She is a team player who is always willing to go the extra mile to ensure project success.