About

Abhijna Balu is a highly skilled CPU Performance Architect at Google with over 5 years of relevant experience in the field. Currently working as a Senior CPU Silicon Design Engineer at AMD, Abhijna has a strong background in CPU performance correlation for Samsung’s Exynos processors, powering the Galaxy S and Note series. Abhijna's expertise lies in investigating performance differences between an RTL design and a cycle-accurate performance model while ensuring that the models correlate with high accuracy on workloads of interest, in terms of CPU cycles and performance counters (PMU). Abhijna has also led the correlation efforts for the Micro-Op Cache and has written and maintained micro-benchmarks for stressing performance features of the designs. Abhijna's past experiences include working as a CPU Performance Architecture Modelling Intern at AMD where she was responsible for verifying a subset of hardware performance counter events in the RTL logic of a next-generation CPU core design. She was also involved in performance correlation (model-vs-RTL simulation) using Pipeline Analysis Tools and Synopsys Verdi. Abhijna has a Master's degree from the University of Massachusetts and a Bachelor of Engineering (B.E.) from BNM Institute of Technology. She completed her 12th grade from Sri Kumarans Children's Home Composite PU College and her 10th grade (C.B.S.E) from Sri Aurobindo Memorial School. Abhijna's technical skills include Senior Software Engineering, Mobile, Frontend, Infra, and Test. She is a highly motivated and detail-oriented individual who is passionate about her work and is always striving to learn and grow in her field.