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aditya kodali
staff engineer
About
Aditya Kodali is a highly skilled and experienced staff engineer with over 14 years of experience in the semiconductor industry. He is currently employed at Qualcomm, where he holds the position of staff engineer. In this role, he is responsible for designing and implementing complex semiconductor solutions for various applications. Prior to his current role, Aditya worked as a senior physical design engineer at Broadcom, where he was responsible for designing and implementing high-performance semiconductor solutions for networking and communication applications. He also worked as a physical design engineer at AMD, where he gained valuable experience in designing semiconductor solutions for microprocessors and graphics processing units. Aditya holds a Bachelor's degree in Electronics and Communication Engineering from VEDA - IIT, Jawaharlal Nehru Technological University. He is a highly motivated and dedicated professional who is committed to delivering high-quality solutions that meet the needs of his clients. He is also a team player who works collaboratively with his colleagues to achieve common goals. Aditya's expertise lies in the areas of physical design, timing closure, power optimization, and chip integration. He has a proven track record of delivering successful projects on time and within budget. He is also knowledgeable in the latest industry trends and technologies, which enables him to stay ahead of the curve and deliver innovative solutions to his clients. Overall, Aditya is a highly skilled and experienced staff engineer who is committed to delivering high-quality solutions that meet the needs of his clients. He is a valuable asset to any organization and is sure to make a positive impact wherever he goes.
Education Overview
• veda iit jawaharlal nehru technological university
Companies Overview
• qualcomm
• broadcom
• amd
Experience Overview
15.5 Years
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Experience
Skills
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application specific integrated circuits
asic
clock tree synthesis
debugging
Design
design rule checking
drc
drc lvs erc ant
eda
floorplanning
functional verification
ic
integrated circuit design
layout versus schematic
lec
logic synthesis
lvs
mvrc
perl
physical design
physical verification
place and route
primetime
rtl coding
rtl design
soc
sta
static timing analysis
system on a chip
tcl
tcl perl cshell
timing
timing closure
verilog
very large scale integration
vlsi
Contact Details
Email (Verified)
adiXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
veda iit jawaharlal nehru technological university
2007 - 2009
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