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Aevin Thomas
Physical Design Engineer at Qualcomm
About
Aevin Thomas is an experienced Physical Design Engineer at Qualcomm with over 6 years of relevant experience in the field of VLSI, ASIC, and SoC design. With a strong background in Verilog, TCL, Perl, C, Synthesis, Static Timing Analysis, and Protocols (AMBA, Wishbone), Aevin is a skilled engineer who has worked on various projects throughout his career. Aevin began his career as a Software Engineer at iLink Systems, where he developed software applications for clients. He then moved on to Si2Chip Technologies as a Design Engineer, where he gained experience in VLSI and ASIC design. Currently, Aevin is working at Qualcomm as a Physical Design Engineer, where he is responsible for designing and implementing complex SoC systems. Aevin holds a Master of Technology degree in VLSI Design from SRM University, where he gained a deep understanding of the field. He also holds a PG Diploma in VLSI, ASIC design, and verification from RV-VLSI Design Centre, as well as a Bachelor's degree in Electronics and Communication Engineering from Anna University. Aevin's technical skills and knowledge are not limited to his work experience, as he also has experience as a software engineer. He is proficient in various programming languages and has a strong understanding of software development. In summary, Aevin Thomas is an accomplished Physical Design Engineer with a diverse range of skills and experience in VLSI, ASIC, and SoC design. He is a highly motivated individual who is always looking for new challenges and opportunities to learn and grow.
Education Overview
• srm ist chennai
• rvvlsi design centre
• anna university chennai
Companies Overview
• qualcomm
• si2chip technologies
• ilink systems
Experience Overview
7.5 Years
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Experience
Skills
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ASIC
asic
C
C (Programming Language)
C++
Clock Tree Synthesis
Design
Design Rule Checking (DRC)
EDA
eda
Embedded Systems
Field-Programmable Gate Arrays (FPGA)
FPGA
Integration
Layout Versus Schematic (LVS)
Microsoft Office
Perl
Physical Design
Physical Verification
Place & Route
Primetime
Processors
rtl design
Senior Software Engineer
Signal Integrity
SoC
soc
Static Timing Analysis
TCL
Verilog
Very-Large-Scale Integration (VLSI)
VHDL
VLSI
vlsi
Contact Details
Email (Verified)
aevXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXX21Education
srm ist chennai
Master of Technology - MTech
2014 - 2016
rvvlsi design centre
PG Diploma
2011 - 2012
anna university chennai
B.E
2008 - 2011
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