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Alpana Khot
Lead Application Engineer | Physical Design
Education Overview
• arizona state university
• vidyalankar institute of technology
Companies Overview
• cadence design systems
• intel
• university technology office arizona state university
• agc networks
Experience Overview
10.1 Years
Find anyone’s contact
Experience
University Solution Center Assistant
university technology office arizona state university | Tempe
2014 - 2015
Skills
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Active-HDL
Application-Specific Integrated Circuits (ASI
ASIC
Automation
C
C++
Cadence Encounter
Cadence Encounter RTL
Cadence Schematic Capture
Cadence Spectre
Cadence Virtuoso
Cadence Virtuoso Layout Editor
CMOS
Design
Design Rule Checking (DRC)
designer
DRC
Eagle PCB
EDA
eda
Electronics
Embedded Systems
Hardware
hspice
Keil
Layout Versus Schematic (LVS)
LVS
Matlab
Microcontrollers
Microprocessors
ModelSim
Multisim
Perl
Perl (Basics)
Physical Design
Physical Verification
Programming
Proteus
RTL Coding
RTL to GDSII Flow
RTL Verification
SoC
SPICE
SPICE Circuit Simulator
Synopsys Primetime
System on a Chip (SoC)
System Verilog
SystemVerilog
Verilog
Very-Large-Scale Integration (VLSI)
VLSI
Xilinx ISE
Contact Details
Email (Verified)
alpXXXXXXXXXXXXXXduMobile Number
+91XXXXXXXXXXEducation
arizona state university
Master of Science (M.S.)
2014 - 2015
vidyalankar institute of technology
Bachelor of Engineering (B.E.)
2008 - 2012
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