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amar gulhane
senior staff engineer
About
Amar Gulhane is a highly experienced Senior Staff Engineer with over 18 years of experience in the field of IC design engineering. Currently working as a Principal IC Design Engineer at Broadcom, Amar has also held the position of Senior Staff IC Design Engineer at the same company in the past. Prior to joining Broadcom, Amar worked as a Senior Design Engineer at Freescale Semiconductor. Amar holds a Bachelor's degree in Electronics and Telecommunication Engineering from Rani Durgavati Vishwavidyalaya in Jabalpur, Madhya Pradesh, India. He also holds a Master's degree in Electrical Engineering from Wright State University in Dayton, Ohio, United States. With his extensive experience in IC design engineering, Amar has developed expertise in various areas, including digital design, RTL coding, verification, synthesis, and timing closure. He has worked on several complex projects throughout his career, delivering high-quality results within tight deadlines. Amar is a highly motivated and detail-oriented professional, with excellent problem-solving skills. He has a proven track record of collaborating effectively with cross-functional teams, including hardware and software engineers, project managers, and customers. Amar is also a strong communicator, with the ability to explain complex technical concepts to both technical and non-technical stakeholders. Overall, Amar Gulhane is a highly skilled and experienced Senior Staff Engineer with a passion for IC design engineering. With his strong technical expertise, collaborative approach, and excellent communication skills, he is a valuable asset to any organization in the semiconductor industry.
Education Overview
Companies Overview
• qualcomm
• broadcom
• cadence design systems
• defense research and development organisation
Experience Overview
19.7 Years
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Experience
Skills
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asic
circuit design
Design
eda
ic
logic synthesis
low power design
microprocessors
physical design
power analysis
primetime
rtl design
semiconductors
soc
static timing analysis
tcl
timing closure
verilog
vlsi
Contact Details
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+91XXXXXXXXXXEducation
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