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Amarnath Mahadevuni

Senior Design Verification Engineer at NVIDIA

Contact Amarnath

Education

texas am university

iit roorkee indian institute of technology roorkee

sri chaitanya juinior kalasala

Companies

nvidia

texas am university

cadence design systems

Experience

7.2 Years

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Experience

Senior Design Verification Engineer

nvidia

2018 - Present

Graduate Student

texas am university | Bryan/College Station, Texas Area

2015 - 2018

Software Engineer

cadence design systems | Noida

2013 - 2015

Skills

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ASIC Design and Verification

C

C++

Cadence Spectre

Design

EDA

Field-Programmable Gate Arrays (FPGA)

FPGA

Hardware

infra

Infrastructure

IP

Linux

MATLAB

sas

Specman e

SPICE

Static Timing Analysis

storage

SystemVerilog

test

Universal Verification Methodology (UVM)

UVM

Verilog

Verilog RTL Design

Very-Large-Scale Integration (VLSI)

Contact Details

Email (Verified)

amaXXXXXXXXXXXXXXXXom

Mobile Number

+91XXXXXXXXXX

Education

texas am university

Master’s Degree

2015 - 2018

iit roorkee indian institute of technology roorkee

Bachelor's Degree

2009 - 2013

sri chaitanya juinior kalasala

High School

2007 - 2009

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