About

Ameya Patil is a Staff Digital Design Engineer at IQ-Analog Corporation with a passion for high speed mixed signal ASIC designs, RTL modeling and verification, computer hardware and architecture, low power abstraction, and multi-rate DSP. With a skill set that includes hardware languages such as VHDL, Verilog, and System Verilog, ASIC RTL modeling and simulation using Cadence, ModelSim, Synopsys, and Aldera Riviera, and programming and scripting languages such as C, C++, Java, Linux Bash, PERL, Tcl, and Matlab, Ameya is a highly skilled engineer with expertise in EDA tools, packages, and simulation environments such as Cadence Virtuoso/ICFB, Spectre, Hspice, and OpenOCD. Ameya's current role at IQ-Analog Corporation involves working on subsystem RTL design, top-level integration, and functional verification of custom feature DSP IP cores and full chip processor-based SoCs for high-speed configurable data converter ASICs. He also focuses on Lint, DFT/ATPG vector gen, Burn-in, logic synthesis, constraints development, and STA to meet timing and coverage requirements. Prior to joining IQ-Analog Corporation, Ameya worked as a Grader at UC Irvine, creating solution sets, grading papers, and projects for under grads, and as a Hardware Engineering Intern at Signal Laboratories, Inc., where he worked on electrical schematic design, simulation, prototyping, and testing of real-time wireless projects. Ameya holds a Master's Degree in Electrical Engineering (Circuits and Devices) from the University of California and a Bachelor's Degree in Electronics and Communications Engineering from R. V. College of Engineering, Bangalore. With almost 7 years of relevant experience, Ameya is a skilled designer with expertise in Java, integration, and test.