About

Amit J. is an experienced FPGA/Systems Engineer currently working with a startup. With over 7 years of relevant experience, Amit has worked with Xilinx in the past as a Senior Design Engineer and Design Engineer II. At Xilinx, Amit was involved in various projects related to FPGA architecture, validation, and bring up. He has extensive knowledge of FPGA bootup and configuration, hardware to software modelling, and various blocks of FPGA. He has also worked on creating solutions for Emulation platform, DAC/ADC, Test and measurement on ACAP (Adaptive Compute Acceleration Platform). Amit has designed de-skew algorithms using soft logic for MIPI v1.2 for Xilinx Ultrascale Plus. He has also worked on generating timing arcs required for Vivado SW and created validation scripts for the arcs generated using perl. Additionally, he has worked with Advance IO Wizard and Memory IP Group (MIG) of Vivado Design Suite to create sub-core routines in TCL to auto-generate configurations according to user interface requirements and IO pin selection for PHY. Amit has designed custom soft CDR (clock data recovery) for Asynchronous Interfaces (SGMII, 1000base-x, Video 7:1, Video 14:1) to track VT (voltage temperature) variations, PPM difference in RX and TX clock, unknown phase difference, and emulated on Xilinx Ultrascale plus FPGA. He has also added extended delay line calibration state machine to BISC (Built In Self Calibration) block for Memory PHY design such that VT (Voltage Temperature) variation can be handled for slower data rates. Amit has a Master's degree in Computer Engineering from the University of Southern California and a Bachelor's degree in Electrical and Electronics Engineering from NIT Tiruchirappalli. His tech stack includes test.