About

Amrita Patil is a highly experienced Formal Verification Engineer with over 12 years of relevant experience in the field. Currently working as a Sr Principal Software Engineer at Cadence Design Systems, she is responsible for pushing the boundaries of the Formal Verification world. Amrita has previously held several key positions at Cadence Design Systems, including Software Engineering Manager and Principal R&D Engineer. In her role as Software Engineering Manager, she was responsible for managing and leading a team of engineers, ensuring that projects were delivered on time and to the highest standards. As a Principal R&D Engineer, she was involved in the development of Assertion Based VIPs for Formal Verification, showcasing her expertise in the field. Amrita holds a B.E. (Hons.) degree in Electrical and Electronics from Birla Institute of Technology and Science (BITS), which she completed in 2011. Her education and experience have equipped her with the skills and knowledge required to excel in her current role. As a Software Engineer and Senior Software Engineer, Amrita has developed a strong tech stack that includes expertise in Formal Verification, Verification IP, and SystemVerilog. Her extensive experience and knowledge of the field make her a valuable asset to any organization. Overall, Amrita Patil is a dedicated and experienced Formal Verification Engineer who has made significant contributions to the industry. Her expertise and passion for the field make her a valuable asset to any organization looking to push the boundaries of Formal Verification.