About

Ankur Vaish is a Senior ASIC Design Verification Engineer at Google with over 12 years of experience in design verification. He has a proven track record of architecting and developing constrained random coverage-driven UVM-based testbenches from scratch. Ankur is an expert in PCIe Protocol, ranging from Gen 1 to Gen 6, and has experience in leading verification teams. Ankur has experience in all levels of verification, including IP level verification, subsystem level verification, and SoC level verification. He has experience in writing VIPs for simulation as well as emulation. Ankur is proficient in UVM, Verilog/System Verilog, and Synopsys/Mentor/Cadence tool sets. He has worked in multi-team and multi-site environments, demonstrating his ability to collaborate effectively with others. Currently, Ankur is working at Google as a Senior ASIC Design Verification Engineer. Prior to this, he worked at Cadence Design Systems as a PCIe IP Verification Lead, where he led the verification effort to verify Gen 5/Gen 6 DLL Layer for Cadence's PCIe HPA Gen 5/Gen 6 IP. He also worked at Mentor Graphics as a PCIe Technical Lead. Ankur holds a B.Tech in Electronics and Communication from IIIT, completed in 2010, and an Intermediate degree in Science from Dewan Public School, completed in 2006. He has relevant experience of 12.27 years and is proficient in senior software engineering. Overall, Ankur is a highly skilled and experienced ASIC design verification engineer with expertise in PCIe Protocol and a proven track record of leading verification teams. His ability to develop UVM-based testbenches from scratch and write VIPs for simulation and emulation make him a valuable asset to any team.