About

Apurv Panchal is an experienced ASIC Physical Design Engineer currently working at Qualcomm. With a relevant experience of 3.78 years, he has previously worked as a Physical Design Intern at Qualcomm and as a Graphic Hardware Intern at Intel. Apurv holds a Bachelor's degree in Electronics and Communication Engineering from Vishwakarma Government Engineering College, Ahmedabad, India, and is currently pursuing a Master's degree in Electrical Engineering from the University of Houston, Clear Lake, Texas, United States. As an ASIC Physical Design Engineer, Apurv has a strong understanding of the design flow from RTL to GDS, including floor planning, power planning, placement, clock tree synthesis, routing, and physical verification. He has experience with industry-standard EDA tools such as Cadence, Synopsys, and Mentor Graphics, and has worked on multiple tape-outs for high-performance designs. Apurv is a highly motivated and detail-oriented individual with excellent problem-solving skills. He has a strong ability to work independently as well as in a team environment, and is always ready to take on new challenges. With a passion for learning and a keen interest in the latest technologies, Apurv is committed to delivering high-quality results in his work.