About

Arjun Nag is a versatile Senior Design Verification Lead with over 8 years of experience in the field of VLSI. He possesses hands-on experience in System Verilog, Verilog, and VHDL, and is well-versed in creating OVC's and UVC's. Arjun has a good understanding of SoC level Test bench Architecture and is skilled in RTL-C co-simulation on HLS tool. He is an expert in Processor boot flows and Verification flow at SoC level. Arjun has excellent knowledge of FPGA, ASIC, and SoC Design & Verification Life Cycles. He has an excellent understanding of protocols like PCIe (Gen 2 & 3), UART, SPI and Compression/decompression Engine, QSPI, AMBA AXI, SMB & HTP. He is proficient in both functional and gate level simulations and possesses hands-on experience in Emulating complex SoC designs, Interface Build-up, and Debugging. He is also skilled in Design Partitioning and Trimming. Arjun has hands-on working experience of Mentor Veloce Quattro 2 & MAXIMUS Emulators. He has experience in Emulating Complex memory controllers and functional IP blocks in In Circuit Emulation (ICE) and TBX Modes. He is well-versed in setting up software top and hardware top in a Top Level Emulation test bench. Arjun is a quick learner and is willing to learn new skills. He has excellent communication & articulation skills, interpersonal relations, analytical skills, hardworking, and result-oriented as an individual and in a team. He has excellent debugging and documentation skills and is familiar with Configuration Management tools like Tele logic DOORS and CM Synergy tools. Arjun's specialties and highlights include SystemVerilog, Verilog, VHDL, UVM, FPGA, ASIC, SOC, Active-HDL 8.3, Rivera Pro 2019.10, Xilinx ISE suite 11, Model Sim 10, Questa Sim12.c, CadenceIES, Synopsys VCS, Rapid Prototyping & Emulation, and Hardware Software Co-Verification. Currently, Arjun is working as a Senior Design Verification Lead at Tata Consultancy Services. He is leading a team of 10 in the IP & SoC Verification of QSPI Flash Controller project for a domestic RISC-V based Processor company. He is responsible for understanding the complete QSPI protocol, generating Verilog equivalents of QSPI design using the B