About

Arokia Rinaldo Andrew is an experienced ASIC Verification Engineer currently working at Palo Alto Networks. With a Master's Degree in Electrical Engineering from the University at Buffalo and a Bachelor's Degree in Electronics and Communications Engineering from Anna University, Arokia has been in the industry for 7.78 years. Arokia's expertise lies in Digital Design and Verification, with a keen interest in Design Verification, High-Performance Architecture, PCIe, and SR-IOV. He is proficient in Digital design and Verification using System Verilog and UVM. He has worked on PCIe verification of Endpoint, DMA, and SR-IOV. Arokia has a solid understanding of Computer Architecture concepts such as Pipelining, Out of Order CPU, Caches, Load Store Queues, Branch prediction, Multi-threading, and Coherence. He is also well-versed in Static Timing Analysis (STA), Clock Tree Synthesis (CTS), Low power & High-Speed CMOS design, IC Design flow, and device physics. Arokia has experience with embedded system design using FPGA and microprocessors (MIPS, ARM), RTOS, and scripting. He is skilled in programming languages such as Verilog, System Verilog, C, and C++. He is proficient in scripting languages like Shell, Python, and Perl. He has also worked with protocols such as PCIe and SR-I/O V and has experience with MIPS ISA. Prior to joining Palo Alto Networks, Arokia worked as a Staff Verification Engineer at Marvell Semiconductor and as an SoC Design Engineer at Intel Corporation (Altera). At Intel, he was involved in the Design Verification of PCIe IP for Intel FPGA. Arokia is currently working as a Senior Staff ASIC Verification Engineer at Palo Alto Networks, where he continues to apply his skills and expertise in Digital Design and Verification. He can be reached at arokiarinaldo@gmail.com.