About

Arooj Asif is an experienced FPGA Firmware Engineer with a hands-on experience in RTL development, HDL implementation, simulation, and verification of digital designs. She has extensively worked with synthesis and analysis tools such as Xilinx ISE, Vivado Design Suite, and ModelSim for different FPGA families. Arooj is proficient in VHDL/Verilog programming and has a relevant experience of 4.27 years in the field. Currently, Arooj is working as an FPGA Firmware Engineer at DESY, where she is responsible for designing and implementing FPGA firmware for various projects. Prior to this, she worked as a Master Thesis Student and a Working Student at Technical University Munich, where she designed and developed scalable monitoring systems for FPGA prototypes of multiprocessor SoCs. She emulated the data characteristics of the target ASIC and built a high-level API for software-hardware interface to provide run-time software access. Arooj also diagnosed reliability degradation of FPGA prototypes and emulated ASIC aging monitors to determine the remaining time slack. She tested these designs for reference designs using tools such as MATLAB, C, Python, VHDL, Vivado Design Suite, Xilinx Virtex 7 FPGA (VC707) board, Xilinx proFPGA board, and Tcl. Arooj holds a Master's degree in Communication Engineering from Technical University Munich and a Bachelor's degree in Electrical Engineering from National University of Science and Technology. She has a good understanding of Python and has used it in her projects.