About

Arunachalam Annamalai is a highly skilled and results-driven Computer Engineer with over 13 years of experience in various aspects of CPU design. He specializes in Performance Modeling/Architecture, physical design/implementation, and research on heterogeneous architectures for energy efficiency. Currently, he is working as a Senior Member of Technical Staff at AMD, where he is a part of the Cores Performance team. Arunachalam has several notable accomplishments to his credit. He successfully led the RTL-performance correlation efforts across 3 sites for the very latest Zen 3 core. He is also leading a team to develop infrastructure and strategic approaches to quantify and improve functional and speed path coverage of cache resident test patterns used on testers. Additionally, he has modeled a complete L2 controller from scratch, meeting tight deadlines. Arunachalam has also contributed significantly to research on asymmetric multicores for energy efficiency, resulting in 12 publications in refereed conferences and journals. As a Graduate Research Assistant at the University of Massachusetts Amherst, he explored dynamic runtime solutions assisted by hardware performance counters to improve performance/power efficiency of Asymmetric Multicore Processors capitalizing on program phases. He also served as a Graduate Teaching Assistant for the course "Introduction to Computer Architecture" under Prof. Israel Koren. Arunachalam holds a Master of Science (M.S) in Computer Engineering from the University of Massachusetts Amherst and a Bachelor of Engineering (B.E) in Electronics and Communication from Madras Institute of Technology, Anna University. He has a diverse tech stack that includes Software Engineering, testing, frontend development, research, and infrastructure. Overall, Arunachalam Annamalai is a highly skilled and accomplished Computer Engineer with a proven track record in CPU design, research, and development.