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Arushi Jain
SoC Logic Design Engineer @ Intel | ASIC Design
About
Arushi Jain is a highly skilled SoC Design Engineer with a Master's degree in ICVLSI from the University of Michigan, Ann Arbor. Currently working at Intel Corporation, Arushi is responsible for designing and integrating complex systems-on-chip (SoC) products. With over 5 years of relevant experience, Arushi has a deep understanding of the hardware design process and has worked on a wide range of projects across different domains. Arushi started her career as a Graduate Technical Intern at Intel, where she worked on integrating and architecting Post-Si debug models across client and SoC products. Later, she joined Mentor Graphics as a Senior Member Of Technical Staff, where she worked on developing and testing hardware emulation models for complex SoC designs. Her strong technical skills and attention to detail have made her an invaluable asset to any team she has worked with. Arushi's educational background includes a Bachelor of Engineering (B.E.) in Electrical and Electronics Engineering from DTU and a Master's degree in Electrical and Computer Engineering from the University of Michigan. Her technical expertise includes software engineering, and she has a solid understanding of programming languages such as C, C++, and Python. Arushi is a highly motivated and detail-oriented individual who is always eager to learn and take on new challenges. She is a team player who is skilled at collaborating with cross-functional teams to deliver high-quality products on time. With her strong technical skills and experience, Arushi is well-equipped to take on any complex SoC design challenge.
Education Overview
• university of michigan
• dtu delhi college of engineering
• apeejay school pitampura delhi
Companies Overview
• intel
• mentor graphics
• ieee dtu
• cadence design systems
• tpddl
Experience Overview
6.8 Years
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Experience
Skills
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asic
C
C++
Debugging
Design
designer
Frontend
Hamster VHDL-AMS
Integration
IP
LaTeX
Lint
Logic and Reasoning
PCIe
Questa
rtl design
soc
Software Engineer
SystemVerilog
Universal Verification Methodology (UVM)
VCS
Verdi
Verilog
VLSI
Contact Details
Email (Verified)
aruXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
university of michigan
Master's degree
2019 - 2020
dtu delhi college of engineering
Bachelor of Engineering (B.E.)
2012 - 2016
apeejay school pitampura delhi
1998 - 2012
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