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Arvind Puthige
Memory Application Engineer @Samsung
About
Arvind Puthige is an enterprising and aspiring polymath with a passion for solving complex challenges with significant outcomes. He is currently working as a Staff Memory Design Engineer at IBM and has 3.94 years of relevant experience in the field. Arvind's expertise lies in memory application engineering, where he has been instrumental in developing analysis chains for test time and pass rate analysis, MBIST characterization, and yield engineering. He has also worked as a Yield Engineer and Data Analyst at AMD, where he analyzed test insertion data for EPYC server level 'Starship' processor with 7nm Core die. Arvind has a Master of Engineering degree in Electrical and Computer Engineering from Cornell University, where he developed a strong foundation in his field. He also has a Bachelor's degree in Electrical, Electronics, and Communications Engineering from SRM University. Additionally, he completed a Special Student Program in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. Arvind is proficient in various technologies, including SQL, machine learning, and test. He has also worked on open-source data analysis tools such as KNIME. Arvind is a proactive and results-driven professional who is always looking for new challenges. He is passionate about his work and thrives in a fast-paced and dynamic environment. With his strong technical skills and analytical mindset, he is an asset to any organization.
Education Overview
• cornell university
• massachusetts institute of technology
• srm university
Companies Overview
• ibm
• intel
• amd
• massachusetts institute of technology
• drdo
Experience Overview
4.8 Years
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Experience
Undergraduate Researcher @ MIT Tata center for Technology and Design
massachusetts institute of technology | Cambridge, MA
2016 - 2016
Project Intern @ Advanced Numeric Research and Analysis Group (ANURAG)
drdo | Hyderabad Area, India
2015 - 2015
Skills
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Analog Circuit Design
Assertions
C
C++
Cadence Schematic Capture
Cadence Virtuoso
Cadence Virtuoso Layout Editor
CPU design
Data Analysis
Design
Digital Circuit Design
Electrical Troubleshooting
Electronics
Embedded Systems
Formal verification
Hardware Development
Java
Layout Design
Leadership
Linux
Machine Learning (ML)
Management
Matlab
Microsoft Excel
Microsoft Office
Microsoft PowerPoint
Microsoft Word
open source
P&R
Performance Analysis
Physical Design
Programming
Python
Python (Programming Language)
RISC-V
Routing
Scripting
Semiconductors
Static Timing Analysis
Synthesizing
System on a Chip (SoC)
System Verification
SystemVerilog
Technical Documentation
test
Test planning
Test Procedures
testing
Verilog
Very-Large-Scale Integration (VLSI)
VHDL
Contact Details
Email (Verified)
arvXXXXXXXXXXXXXXXXXXXomMobile Number
+91XXXXXXXXXXEducation
cornell university
Master of Engineering - MEng
2017 - 2019
massachusetts institute of technology
Special Student Programme
2016 - 2017
srm university
Bachelor’s Degree
2013 - 2017
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