About

Ashvini Sharma is a Senior Lead Engineer in SoC and IP DV and DE Architecture, with over 12 years of relevant experience in the field. He is currently employed at Qualcomm, where he holds the position of SoC Design and Verification Senior Lead Engineer. Ashvini has also worked as a Senior Design and Verification Engineer at Intel and as an MTS at Chelsio Communications. Ashvini has extensive knowledge of Verilog Hdl, System Verilog, VMM, and UVM. He is well-versed in microarchitecture of complex and highly integrated deep submicron complex IC high frequency and low power emphasis. Additionally, he has worked on IEEE 802.x compliant Ethernet Protocol Processing engine and very high-speed next-gen Gigabit Ethernet Card. He has also designed complex memory-centric DE architecture that acts as the backbone of TCP/IP offloading engine compliant with different RFC and STD with complex algorithms. Ashvini has a functional knowledge of DDR3 | DDR4(*) SDRAM and PHY IP core. He has worked on Design For Debug (DFD) OEM Specific Complex MicroArchitecture supporting Multi SoftCores and HardCores For Pre/Post Silicon Debug. He has also worked on CoreSight ARM Debug Architecture. Ashvini is well-versed in constraint random coverage-driven IP verification and implementation using HVL SV-VMM, gate-level simulation, synthesis logic families Fpga/Emulation for pre-silicon ASIC prototype validation, multigate Mosfet, Cmos & Bicmos reliability, process technology, and design architecture. Ashvini holds a bachelor's degree in Electronics & Communication from Dr. M G R Educational & Research Institute, where he graduated in 2010. He also attended Kendriya Vidyalaya from 1992 to 2004. Overall, Ashvini is a highly skilled and experienced engineer with a strong background in SoC and IP DV and DE Architecture. He possesses a wide range of technical skills and experience in leading and cutting-edge technology, planning, architecture, implementation, design, and verification of complex leading and cutting-edge technology.