About

Avinash Pandey is a Formal Verification Engineer at Qualcomm with over 7 years of relevant experience in the VLSI domain. He has a strong understanding of HDLs, including Verilog, and HVLs, such as System Verilog. Avinash is also proficient in UVM Basics for TB Methodology and scripting languages such as Perl, C, and Shell. He has worked with EDA tools such as VCS, SPYGLASS, Bugscope, and Jasper-Gold. Additionally, Avinash has experience working with protocols such as AMBA-AHB, APB, and CHI. Currently, Avinash is working as a Senior Lead Engineer at Qualcomm. Before joining Qualcomm, he worked as a Software Engineer at Cadence Design Systems and as a Lead Engineer at HCL. Avinash completed his M.Tech in VLSI Design from Galgotia University in 2015. Avinash's technical skills include Senior Software Engineer and Software Engineer. He is a dedicated team player with a passion for solving complex problems and delivering high-quality results. His experience in the VLSI domain has equipped him with a deep understanding of the industry's best practices and trends. Overall, Avinash is a highly skilled Formal Verification Engineer with extensive experience in the VLSI domain. He is an asset to any team and consistently delivers exceptional results.