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Avisekh Ghosh
RTL Design Engineer @ TI
Education Overview
• dtu delhi technological university
• kendriya vidyalaya ina colony
• kendriya vidyalaya
Companies Overview
• texas instruments
• sifive
• stealth startup
• technobyte
• dsad research group
• airports authority of india
Experience Overview
3.8 Years
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Experience
Skills
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Application-Specific Integrated Circuits (ASI
Cadence Spectre
Cadence Virtuoso
Design
DFT
Functional Verification
Integration
IP
LEC
Lint
Logic and Reasoning
Logic Synthesis
Microarchitecture
Mixed-Signal Integrated Circuits
Modeling
Python
Python (Programming Language)
RTL Coding
RTL Design
rtl design
Static Timing Analysis
SystemVerilog
TCL
test
Timing Closure
Universal Verification Methodology (UVM)
Verilog
Vim
Contact Details
Email (Verified)
4viXXXXXXXXXXXXomMobile Number
+91XXXXXXXX04Education
dtu delhi technological university
Bachelor of Technology
2017 - 2021
kendriya vidyalaya ina colony
High School
2015 - 2017
kendriya vidyalaya
Matriculation
2010 - 2015
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