About

Avner Fish is a highly experienced Senior Design Verification Engineer at SEAKR Engineering, Inc. with over 16 years of experience in the field of emulation and verification. He has a deep understanding of working with designs that include embedded processors and DSPs and is proficient in building and debugging emulation models and test benches for them. Avner specializes in transaction-based emulation and has been responsible for creating several UVM/C/SystemC co-modeling solutions. Avner has a strong grasp of chip architecture and software and is skilled at debugging issues that occur at the boundary between hardware and software. He has implemented his experience to build full chip emulation systems from scratch up to booting Linux OS on the emulated models, and migrating simulation test benches to emulation. His core disciplines include emulation, transaction-based verification, functional verification, ASIC design, ARM architecture, AMBA AHB bus, Altera, and Xilinx FPGAs. Avner is well-versed in several coding languages such as C++, SystemC, System Verilog, UVM, Assembler (ARM, MIPS), TLM, PLI, VHDL, and Verilog. He is currently upgrading his verification skills at UCSC extension. With his extensive experience, Avner has worked with several leading companies in the past, including Cadence Design Systems and Mentor Graphics Corporation. Avner has a strong educational background, having completed his education from the University of Texas at Austin and UVM Course. He is proficient in several technologies, including Test and C. Overall, Avner has 20.44 years of relevant experience in the field of emulation and verification, making him a valuable asset to any organization.