About

Balaji B. is an experienced Analog Layout Engineer with over 7 years of experience in Custom Analog, Mixed signal and IO layout design. He has worked on a range of projects including Thermal sensor (10nm), CM_AFE top level (40nm, SerDes), TX_AFE top level (28nm_SerDes low power), GPIO'S (40nm), PLL (40nm), OP_AMP (40nm), Band-gap (40nm), PowerSupply Detect (55nm) Standard cells (16nm, 55nm, 130nm), and VCO (55nm). He is experienced in chip level tape out and has a deep understanding of the design process. Currently, Balaji is a Member of Technical Staff at Analog Port, where he is responsible for designing and implementing analog layouts for various projects. Prior to this, he worked at Altran as an Analog Layout Engineer, where he was responsible for designing and implementing analog layouts for various projects. Balaji started his career as a Layout Trainee at Insistute of Silicon System, where he gained hands-on experience in layout design. He has a strong technical background and is proficient in various software tools. With a relevant experience of 8.61 years, Balaji has a proven track record of delivering high-quality work on time. He is a team player and has excellent communication skills. He is passionate about his work and is always looking for ways to improve his skills and knowledge.