About

Bandaru Venkatesh is a Senior Formal Verification Engineer at Intel Corporation's Formal Verification Central Tech Office team. With over 4 years of relevant experience, he specializes in verifying Intel IP's using formal verification methodologies. Venkatesh's technical expertise includes writing assertion-based verification testbenches, formal modeling, debugging on RTL, formal abstractions, and helping other team members on the topics above. He is a valuable asset to the team, as he is able to apply his knowledge and skills to ensure that Intel's products meet the highest standards of quality and reliability. Prior to joining Intel, Venkatesh worked as an Application Engineer I at Synopsys, where he worked with customers to address queries related to VC formal tool, formal methodology, debugging, and convergence. He has also worked on different formal methods like Property Verification, Data Path Verification, Formal Coverage, and VC Formal Sign-off flow with various customers. Additionally, he worked as a Product Validation for various features of VC Formal and Hector tools and verified data path designs using HECTOR with a very good knowledge of floating-point arithmetic. Venkatesh has also completed a Software Engineering Internship at Samsung, where he developed a chatbot-based Android application for scheduling meetings for users. Venkatesh holds a Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering from iiit, as well as intermediate education from Sri Chaitanya Junior College and a 10th class certificate from Hayathnagar Public School. Overall, Venkatesh is a skilled and experienced engineer who is dedicated to ensuring the highest quality of Intel's products through his expertise in formal verification methodologies.