About

C Gangadhara Reddy is an experienced MTS Silicon Design Engineer at AMD with over 8 years of experience in the industry. Currently, he is working as a Lead Design Verification Engineer at Cadence Design Systems, where he is responsible for ensuring the correctness and completeness of designs before they are sent for fabrication. Gangadhara Reddy has a strong background in VLSI system design and has worked on various projects related to the same. He has experience in developing and implementing design verification plans, test benches, and test cases for complex designs. He is also skilled in using industry-standard tools like SystemVerilog, UVM, and Verilog for design verification. Prior to his current role, Gangadhara Reddy worked as a Senior Design Verification Engineer at Cadence Design Systems, where he gained extensive experience in design verification and validation of complex designs. He has also worked on projects related to low power design, clock domain crossing, and formal verification. Gangadhara Reddy holds a Master's degree in VLSI System from NIT Trichy, where he gained a strong foundation in the field of VLSI design and verification. He is a highly motivated individual who is passionate about his work and is always eager to learn new things. In summary, Gangadhara Reddy is an experienced MTS Silicon Design Engineer with a strong background in VLSI system design and design verification. He is skilled in using industry-standard tools and has worked on various projects related to low power design, clock domain crossing, and formal verification. He is a highly motivated individual who is passionate about his work and is always eager to learn new things.