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chia chang
senior digital design engineer
About
Chia Chang is a seasoned Senior Digital Design Engineer with over a decade of experience in the field. Currently, he is working at Qualcomm as a Senior Digital Design Engineer, where he is responsible for designing and developing digital circuits and systems for wireless communication devices. Prior to joining Qualcomm, Chia worked as an FPGA Prototyping Intern at Nvidia and as an ASIC Design Engineer at UCLA High-Speed Electronic Lab. During his tenure at Nvidia, he gained valuable experience in field-programmable gate array (FPGA) design and prototyping. At UCLA High-Speed Electronic Lab, he worked on designing and implementing complex digital circuits and systems for high-speed electronic devices. Chia holds a Bachelor's and a Master's degree in Electrical Engineering from the University of California, Los Angeles (UCLA). During his time at UCLA, he gained a strong foundation in digital design, computer architecture, and VLSI design. With over 10 years of relevant experience, Chia has developed a deep understanding of digital design principles and methodologies. He is skilled in using industry-standard tools and software for digital design, including Verilog, VHDL, and SystemVerilog. Additionally, he has experience in designing complex digital systems for wireless communication devices, including 5G and LTE. Chia is a highly motivated and results-driven professional who is passionate about digital design. He is a team player and possesses excellent communication and interpersonal skills. His expertise in digital design and his ability to work collaboratively with cross-functional teams make him an asset to any organization.
Education Overview
• university of california los angeles
Companies Overview
• qualcomm
• nvidia
• ucla high speed electronic lab
• kawasaki microelectronics
Experience Overview
11.4 Years
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Experience
Skills
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algorithms
application specific integrated circuits
asic
c
c++
cadence spectre
cadence virtuoso
Design
encounter
fpga
logic design
matlab
mixed signal
pll
primetime
Prototyping
rtl coding
serdes
simulink
static timing analysis
verilog
Contact Details
Email (Verified)
fraXXXXXXXXXXXXXXXXXXomMobile Number
+18XXXXXXX77Education
university of california los angeles
2011 - 2013
university of california los angeles
2007 - 2011
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