About

Darpana Pendyala is a highly experienced Senior Timing Design Engineer currently working at Qualcomm. With over 6 years of relevant experience in the industry, Darpana has established herself as a skilled and knowledgeable professional in the field of timing design engineering. Prior to her current role, Darpana has worked as an Analog Design Engineer and Custom Library FDK Intern at Intel. Her experience at Intel has allowed her to gain valuable insights into the intricacies of the industry and develop a deep understanding of the design process. Darpana holds a degree in Electrical and Electronics Engineering from the University of Massachusetts Amherst. During her time at university, she gained extensive knowledge and practical experience in the field of electrical and electronics engineering. Her education has equipped her with the skills and knowledge necessary to excel in her current role. As a Senior Timing Design Engineer at Qualcomm, Darpana is responsible for designing and verifying timing constraints for complex digital designs. She collaborates with cross-functional teams to ensure that the designs meet the required specifications and are delivered on time. Darpana is a highly motivated and dedicated professional who is committed to delivering high-quality work. She is passionate about her work and is always looking for ways to improve her skills and knowledge. Her expertise and experience make her a valuable asset to any organization.