About

Devendra Bahadur Singh is a Senior Engineering Manager at NXP Semiconductors with over 21 years of experience in RTL design, multi-FPGA prototyping, SoC emulation, and debug subsystem level bring-up. He has extensive expertise in defining system architecture for prototyping and validation of IP and subsystem, SAS, SATA error injection scripts, and system-level bring-up including debugger bring-up and debug (HW + SW). Devendra has exposure to various protocols such as enterprise storage (SAS, SATA, PCIe), bus architectures (AMBA - AHB, APB, AXI, PLB), DDR memory (DDR1, DDR2, DDR3), low-speed serial (I2C, SPI, UART, JTAG, SWD), and nonvolatile (NAND, NOR). Currently, he is responsible for leading and managing the FPGA based Pre-Si Validation team of IP and subsystems targeted for high-performance Automotive Processors at NXP Semiconductors. He is also responsible for architecting FPGA Pre-Si platforms for Gateway, ADAS (Vision & Radar) domains for datapath and performance validation. Prior to his current role, Devendra worked as a Principal Staff Design Engineer at NXP Semiconductors, where he developed strategy and SoC emulation platforms for Pre-Si validation of Automotive SoCs. He also worked as a Staff Engineer at LSI, where he was part of the post-silicon validation team validating SAS/SATA protocols. Devendra holds a Bachelor of Engineering (BE) degree in E & TC from Savitribai Phule Pune University. He is skilled in senior software engineering and integration and has a strong background in FPGA prototyping, RTL design, and integration.