About

Digvijay Bansal is an experienced ASIC Physical Design Engineer with a strong background in Synopsys tool suite and Redhawk. He is currently working at Synopsys as an ASIC Physical Design Engineer II - Design Implementation, where he is responsible for mixed signal IP implementation (RTL to GDSII) with technology nodes less than 28nm. His work involves synthesis, PnR, timing sign-off closure, DRC/LVS/ERC/DFM cleanup, IR analysis, EM analysis, and release. Digvijay Bansal has a Bachelor's degree (Hons.) in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani. He also holds a Science (PCM) degree from Lal Bahadur Shastri Smarak Javm Senior Secondary School, RK Puram, New Delhi, and a General Studies degree from Bihani Children's Academy, Rajasthan. Prior to joining Synopsys, Digvijay Bansal worked as an ASIC Physical Design Engineer I - Design Implementation at Synopsys and as an Engineering Intern, Memory IP - Physical Design Group at Arm. At Arm, he worked on the analysis of PPA (Power, Performance & Area) for Arm Artisan Memory Compilers for early customer specification estimation. He also developed a custom software solution that automated the PPA trend analysis for memory compilers across all technology nodes, reducing analysis time by 10x and enabling identification of unpredicted behavior with the help of visual plots and spreadsheets. He further enhanced the software to provide comparative PPA analysis for memory compilers across multiple technology nodes and product releases. Digvijay Bansal's technical skills include test, integration, and senior software engineering. He is a skilled professional with 3.86 years of relevant experience.