About

Dinesh Garg is a highly skilled Director of Engineering with over 20 years of experience in the semiconductor industry. He is currently working at Cadence Design Systems as a Software Engineering Director, where he is responsible for driving innovation and automation in the design and verification of Analog IPs. Dinesh has a strong focus on post-layout simulations of Analog IPs, such as SerDes, PLL, DC-DC Converters, and Equalizers. He is known for his ability to deliver first-time-right and robust designs across corners at cutting-edge process nodes based on analytical models. Additionally, Dinesh has extensive experience in custom standard cell foundation IP design, including clock gators, domino logic flops, isolation circuits, and retention flops. He is also skilled in architecture development, layout review, and complete library solutions with characterization and front-end Verilog models. Dinesh's expertise spans from 180nm to 28nm nodes, and he is highly proficient in innovation and acceleration, analog IP design, foundation IP design, automation, and foundation library design and characterization. He is passionate about using his skills to drive innovation and automation in the semiconductor industry. Prior to joining Cadence Design Systems, Dinesh worked at Magma Design Automation as a Principal Product Engineer, where he worked on equation-based analog solver Titan ADX and advanced library tools from Magma, SiliconSmart. He also worked at Synopsys as an R&D Manager II, where he managed a team of engineers working on accelerating different types of digital, analog, and mixed-signal circuits. Dinesh holds a Bachelor of Engineering degree in Electronics and Electrical Communication from Thapar University. He is highly skilled in AI, Frontend, and Software Engineering. Dinesh can be contacted at hereisdinesh@gmail.com.