About

Divyashree Produ is a CPU Design Engineer at Intel with a Master's degree in Electrical Engineering from the University of Minnesota. She specializes in Circuit Design, Design Automation, and Computer Architecture. Divyashree has a good understanding of VLSI Digital Design concepts and is familiar with optimizing logic for timing and power. She has a conceptual understanding of ASIC design flow and tools, RTL design and synthesis, STA, Formal verification, and Implementation. Divyashree has also worked on EDA algorithms and their implementation. Divyashree has experience in circuit design and implementation of the instruction fetch units of Intel Core. She has also worked as a Component Design Engineer Intern at Intel Corporation where she was responsible for high-speed low power semi-custom circuit design of hierarchical functional unit blocks for the Instruction Fetch Unit. She designed the circuit based on RTL update using in-house tools incorporating power and timing constraints ensuring Formal equivalence. She achieved convergence of the implemented design by performing Static timing analysis and Power analysis. Divyashree has also worked on evaluating ICC II features at Synopsys. Divyashree's interests include Circuit Design, Physical Design and Implementation, and Design Automation. She is proficient in C, C++, and scripting languages like Perl and TCL. Divyashree has experience working with VLSI CAD Tools like Cadence Virtuoso (Layout & schematic), HSPICE, Calibre (LVS/DRC/PEX), CosmosScope, Synopsys VCS, Design Compiler, TetraMAX, Formality, IC Compiler II, and PrimeTime. She is also proficient in scripting languages like PERL, Cadence SKILL, Verilog, System Verilog, TCL, C, Shell scripting, and C++. Divyashree has a Bachelor's degree in Electrical, Electronics, and Communications Engineering from Ramaiah Institute of Technology. She has relevant experience of 4.95 years and is currently working as a SoC Design Engineer at Intel.