About

Feroz Choudhary is an experienced ASIC Physical Design Engineer with a strong background in VLSI and Embedded Systems. He is currently working at Synopsys as an ASIC Physical Design Engineer, handling two blocks for timing analysis, generating ECOs for hold, setup, and TDRC, skew analysis, analyzing cons issues, and reporting for fixes. Prior to this, he worked as a Physical Design Engineer at Qualcomm, where he was responsible for tile ownership, partitioning, floorplanning, feedthrough creation for multiple voltage domains, placements of APMs, ESDs, TCD, anchor buffers, clock and test buffer, PrePlacement cells, Pipelining, and more. Feroz also worked at Intel Israel, where he was responsible for floorplanning, PnR, timing analysis, DRV, IRRV fixes, and scripting. He has experience in tools like Innovus, Calibre, PrimeTime, Fusion compiler, ICC, StarRC, and more. Additionally, he has worked as a Physical Design Engineer at Socdv tech, where he resolved congestion issues, solved dynamic and static IR drop, and balanced skew. Apart from his professional work, Feroz is also a blogger at vlsi-backend-adventure.com, where he shares his knowledge and experience in physical design engineering. He holds a Master of Technology degree in VLSI and Embedded Systems from Reva University, a Bachelor of Engineering degree in Electronics and Telecommunication Engineering from Goa College of Engineering, and a Diploma in Electronics and Communication from Father Agnel Technical Education Complex. With over 3.35 years of relevant experience in backend and software engineering, Feroz is a skilled professional with a passion for physical design engineering. He is a quick learner, a team player, and always strives for excellence in his work.