About

Gaurav Jain is a highly skilled Senior Principal Software Engineer at Cadence Design Systems with over 8 years of relevant experience in developing verification IP for ethernet protocol and other memory models. He has a deep understanding of the IEEE 802.3 spec from 10M to 400G and is well-versed in all the ethernet layers like MAC, RS, PCS, RS-FEC, PMA, etc. Gaurav has gained proficiency in various programming languages such as specman-e, verilog, system-verilog/UVM, and C while developing the VIP. Apart from his expertise in ethernet protocol, Gaurav has also worked on the upcoming USB4 protocol and created the logical layer part of the Verification IP. He has also developed DDR5 data buffer and LRDIMM memory model verification IP in C and verified it using SV/UVM. Currently, he is working on NAND Flash Memory model Verification IP development. Gaurav holds a Master of Technology degree in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani, and a Bachelor's degree in Electronics and Communication from Jamia Millia Islamia. He also attended Cambridge School, Noida. With his strong technical background and extensive experience, Gaurav is a valuable asset to Cadence Design Systems. He is a dedicated and hardworking individual who is always eager to learn and take on new challenges in his field.