About

Harmeet Sobti is a seasoned Principal Engineer and Manager with a wealth of experience in custom analog and digital circuit design, semiconductor device physics, and process technology knowledge in advanced digital/mixed signal finFET nodes. He currently works at Qualcomm as a Principal Engineer/Manager, where he is responsible for design for manufacturing (DFM) test structure design and analysis on leading-edge advanced digital/mixed signal nodes for Qualcomm flagship designs. Harmeet's expertise lies in yield enhancement using DFM EDA software enablement and custom DFM yield learning test structures. He owns full custom analog/mixed signal circuit design, simulation, and layout of the block, as well as test planning, data analysis, and communication to cross-functional fora internal to Qualcomm and as appropriate with partner foundries. He is also responsible for targeted custom critical feature analysis (CFA) code development and deployment to enable product yield enhancement. Prior to joining Qualcomm, Harmeet served as the Director of Product Engineering at Maxim Integrated, where he was responsible for yield enhancement on power management and radio frequency integrated circuits. Harmeet has over 28 years of relevant experience in the industry and has worked on a wide range of projects throughout his career. Harmeet holds a Master of Science in Electrical Engineering, Electro-physics with a focus on Analog Design, Optics, Semiconductor devices from the University of Southern California and a Bachelor of Science in Electronics and Communication Technology from Punjab Engineering College. He is highly skilled in test, frontend, backend, and senior software engineering.