About

Harsh Agrawal is a driven and ambitious Electronics and Communication engineering senior undergraduate with a passion for hardware design and acceleration. With a strong foundation in Digital Electronics and Computer Architecture, Harsh is well-versed in Digital Design using Verilog and SystemVerilog and has adept knowledge of VLSI Physical Design and 8085 Microprocessor. Currently working as a Software Engineer Intern at Xilinx, Harsh has gained experience in Xilinx ISE and VIVADO. He is seeking opportunities in the semiconductor/EDA industry to further his skills and knowledge in the field. Prior to his current position, Harsh worked as an Undergraduate Student Researcher at Synopsys Intelligence Laboratory, Lovely Professional University, Phagwara, where he worked on simulation for various designs of TFETs with different materials like GaAs, SiGe, etc. for their performance enhancement and characteristic development using Synopsys Sentaurus TCAD Device. He also served as the Chief Executive Officer of Renovation Tech Robotics and Aeromodelling, a student organization where he organized various technical events, workshops, and participated in various technical challenges, workshops, seminars, and conferences. Harsh is pursuing a Bachelor of Technology in Electrical, Electronics, and Communications Engineering from Lovely Professional University, where he is expected to graduate in 2022. His tech stack includes Software Engineering and Research Science, and he has relevant experience of 0.87 years. Harsh is a motivated and dedicated individual, always striving to learn and grow in his field.