About

Harsha Garua is a highly skilled Design Verification Engineer with 6 years of experience in SoC/IP Design Verification. Currently working as a Technical Lead at Wipro, Harsha has a proven track record of delivering high-quality verification solutions for complex SoCs. Harsha's expertise lies in SVA, Functional Verification, and SystemVerilog. He has worked extensively on DMA, AXI, MTU, and DFE protocols and is proficient in Verilog, SystemVerilog, Questasim, Simvision, and Verdi. He is also skilled in scripting languages like Perl and Bash, which has helped him to automate the verification process and improve productivity. Harsha's passion for verification started during his internship at Cadence Design Systems, where he gained hands-on experience in SVA, Coverage, and Xcelium. He has also worked as a Lead Engineer at HCL, where he led the verification team and delivered successful projects. Harsha holds a Master of Technology degree in Digital Electronics from Manipal University and a Bachelor of Technology degree in Electronics and Communication from Amity University. He has a relevant experience of 7.36 years and is currently working as a Senior Software Engineer. Harsha is a proactive team player who enjoys working in a collaborative environment. He has excellent communication skills and can effectively communicate complex technical concepts to both technical and non-technical stakeholders. His ability to think critically and solve problems has made him a valuable asset to any team he works with.