About

Harshal Kalyane is a Lead Member of Technical Staff at Rambus with over 5 years of relevant experience in the field of electronics and telecommunications engineering. He is a highly skilled Placement Coordinator with a strong background in Python, C++, Operating Systems, VLSI, FPGA, RTL Design, and Teamwork. Harshal holds a Master of Technology (MTech) degree in Microelectronics and VLSI Design from the prestigious Indian Institute of Technology, Bombay. He also graduated with a Bachelor of Engineering (BE) degree in Electronics and Telecommunications Engineering from Maharashtra Institute of Technology. Prior to his current role at Rambus, Harshal worked as a Senior Design Verification Engineer at Analog Devices and as a SoC Design Engineer at Intel. At Intel, he was responsible for coordinating Design and Architecture teams at multiple sites, ensuring bug-free integration of IPs, and validating Control Status and Functional registers of IPs at Sub-System Level. Harshal was also responsible for validating Acceleration IP at Sub-System Level, volume validation at Sub-System Level, and RDL integration of IPs at Sub-System, validation, and review of their quality with SoC architect. Harshal is a highly skilled software engineer with expertise in Python, test, integration, and senior software engineering. He has received numerous recognitions for finding bugs in IPs at Sub-System and has a strong track record of working on multiple projects and multiple blocks simultaneously, collaborating with multiple teams and individuals. In summary, Harshal Kalyane is a highly skilled and experienced Placement Coordinator with a strong background in electronics and telecommunications engineering. He is a valuable asset to any team and is committed to delivering high-quality results in a timely and efficient manner.