About

Hitesh Gupta is an ambitious and enthusiastic Lead(R&D) at Cadence in San Jose, California. He graduated with a gold medal in Computer Engineering from Delhi College of Engineering in 2019. Hitesh is an aspiring software developer with a passion for taking on everyday EDA challenges. He is quick to learn and enjoys working out algorithms and solutions for computationally intensive data points. Currently, as SDE-2 at Cadence, Hitesh has worked on developing optimization techniques and stabilizing the synthesis tool multithreaded components. He has also worked on intricate flow debugs and multithreaded timing and area/power optimizations. In the past, Hitesh worked as SDE-1 at Cadence, where he was part of the Incremental Optimization R&D team responsible for solving chip-level optimization problems related to flop merging, critical region resynthesis, and timing and area-driven optimizations. Before joining Cadence, Hitesh served as Placement Coordinator at Delhi College of Engineering, where he honed his scheduling and management skills. Hitesh's education history includes a Bachelor of Technology in Computer Engineering from Delhi College of Engineering and CBSE Senior Secondary Examinations in Science from Hansraj Smarak School. Hitesh has a diverse tech stack that includes experience as a software engineer, UI designer, mobile developer, and backend developer. With 3.94 years of relevant experience, Hitesh is a quick learner and a valuable asset to any team.