About

Hitesh K. is a Semiconductor Nanofabrication Engineer with more than 9 years of experience in both academic and industry settings. He has core expertise in Process Integration, Device Design & Tape out engineering, Technology and Product Development, Leading-edge Research, and Manufacturing Operations. Currently, Hitesh is a Senior Process Engineer (Litho & Etch) at Skyline Semiconductors, where he is involved in Fab start-up, device conceptualization to Fab out, and process solutions for CMOS/III-V based device technologies. He has also worked as a Senior Lithography Process Engineer at Skyline Semiconductors, where he was responsible for process development and integration for III-V and Optoelectronics Devices, device conceptualization to Fab out, and application-based tape out engineering solutions. Prior to his work at Skyline Semiconductors, Hitesh was a Member of Process Staff at the Indian Institute of Technology Bombay. In this role, he was lab-in-charge for clean room used in device fabrication, owner of E-beam lithography workstation writing Nanostructures on an assortment of substrates, contributed to in-house process development and policies, and mentored research students/industry user process planning, training, and tool authorization tests, among other responsibilities. Hitesh holds a Bachelor's degree in Electrical, Electronics, and Communications Engineering from IETE and an Engineering Diploma in Electronics and Communications Engineering from Maharashtra State Board of Technical Education (MSBTE), Mumbai. He has experience with integration, research scientist, and GAN technologies. Overall, Hitesh has 10.69 years of relevant experience in the semiconductor industry and is skilled in process integration, device design, and tape out engineering. He is a valuable asset to any company in need of a semiconductor nanofabrication engineer.