About

Hitesh Sharma is an experienced Software Engineer at Intel Corporation with a strong background in RTL Designing and FPGA based high-speed system design. With over 8 years of relevant experience, he has a deep understanding of all the stages of the design cycle, including RTL coding, Verification, IO Planning, Schematic Capture, Signal Integrity Analysis, and PCB Layout. Hitesh has worked with several renowned companies in the past, including the University of Florida and CDAC, where he served as a Research Assistant and Project Engineer, respectively. During his tenure, he worked on various projects, such as IC Piracy Prevention through hardware obfuscation of netlists, Signal Integrity analysis of DDR3-SDRAM, QDRII+ SRAM, and RLDRAMII, and Serial data link and MGH analysis for 10GBASE-T PHY interface. He was responsible for IBIS model creation and validation, timing budget for Read, Write and Address Cycles of the memories, topology extraction and pre-route simulations of Data, Address/Control and Clock signals using Cadence's Allegro SigXp, and SI bus simulations for Read, Write and Address Cycles in Cadence's PCB SI. Hitesh holds a Master's Degree in Computer Engineering from the University of Florida, a PG Diploma in VLSI Design from CDAC acts, Pune, and a Bachelor of Technology (B.Tech.) in Electrical, Electronics and Communications Engineering from PTU. He is proficient in various TechStacks, including Software Engineering and Research Science. Overall, Hitesh is a highly skilled and experienced Software Engineer with a passion for designing complex systems. He is a quick learner, a team player, and always strives to deliver high-quality work.