About

Jalaj Gupta is an experienced Design Verification Engineer with over 9 years of experience in the semiconductor industry. He is currently working as a Member of Consulting Staff at Siemens, where he is involved in IP design verification. Prior to this, he worked as a Lead Design Engineer at Cadence Design Systems, where he was responsible for the design verification of Ethernet 10/25/40/100GBps Verification IP, USB Type C and Power Delivery Verification IP, USB Retimer Model in USB 3.x Verification IP, and USB 3.1 and USB 3.0 Verification IP. Jalaj is skilled in Verilog, System Verilog, UVM, functional verification, constrained random testing, and test environment development. He has a good understanding of various serial and parallel protocols such as 10/40/100G Ethernet, USB 3.1/3.0, USB Re-timers, AMBA AXI-4 AXI-3, CHI, and I2C. Jalaj has a Post Graduation Diploma in VLSI from C-DAC ACTS Pune, India, and a Bachelor of Engineering in Electronics and Communications from GGSIPU Delhi, India. He also completed his intermediate education in Physics, Chemistry, and Maths from Deep Memorial Public School. Jalaj is a highly skilled and experienced engineer with a proven track record in design verification. He is passionate about his work and is always willing to go the extra mile to ensure that projects are completed to the highest standard. His technical expertise and attention to detail make him an invaluable asset to any team.