About

Jay Kapasi is a highly skilled MTS Silicon Design Engineer at AMD with over 11 years of relevant experience. He has a strong interest in Artificial Intelligence, RTL Design, Pre & Post Silicon Validation, SOC Prototyping, Firmware & Software Architecture/Design. Jay has extensive experience in RTL Design, including DSP algorithms such as Filters, FFT, and RADAR, High-Speed interfaces like PCIe, SRIO, Interlaken, USB2, Gigabit transceivers, and Low-Speed interfaces such as SPI and UART. He is also proficient in FPGAs, specifically Xilinx, Microsemi, and Altera. Additionally, Jay has experience in Firmware/Software, including Peripheral drivers such as USB, SPI, I2C, Real-Time DataViewer, and Linux Porting. Jay has a proven track record of success in SOC Prototyping, having worked on projects such as an Automotive Switch, Microsemi FPGA/SoC, and RISCV. He has worked with a set of high-speed peripherals like USB/SDEMMC/GEM and low-speed peripherals like UART/I2C/CAN/SPI/QSPI. Before joining AMD, Jay worked as a Senior Validation Engineer at Microsemi Corporation, where he was responsible for High-Speed FPGA SERDES Validation and Interlaken protocol validation with InterOp. He also worked on SOC Prototyping of a RISC V based multicore (1+4) processor subsystem. Prior to that, he worked as a Module Lead at Mistral Solutions, where he was responsible for Requirement analysis, guiding design engineers, FPGA RTL Design, and Windows driver development for PCIe using WDK to support Autonomous DMA function. Jay holds a Master of Technology (MTech) in VLSI and Embedded Systems from Dhirubhai Ambani Institute of Information and Communication Technology and a Bachelor of Engineering (B.E.) in Information Technology from L.D College of Engineering - Ahmedabad. He also has a strong educational background, including a 12th in Science from Firdaus Amrut High School and a 10th from Lions Club. Jay's Tech Stack includes Integration, which is a testament to his ability to work seamlessly with various teams and stakeholders. Overall, Jay is a highly skilled engineer with a proven track record of success in RTL Design, SOC Prototyping, and Firmware/Software Architecture/Design.