About

Jayadev Devagiri is an accomplished RTL Design Engineer with over 7 years of experience in the VLSI design field. He has worked on a variety of projects, ranging from low power IOT WLAN chips to high-performance discrete graphics SOC teams. Jayadev has a Master's degree in VLSI and CE from IIITH, which has provided him with a strong technical background in VLSI design. Jayadev's notable skills include microarchitecture, all aspects of the VLSI flow, RTL design, verification, emulation, post-Si bring-up, CDC/LINT flow, UPF strategies, and IEEE 802.11 protocol. He is also adept at ECO implementation with FEV clean-up. Currently, Jayadev is working as a Soc Design Engineer at Intel. In this role, he has taken on the challenging task of RTL development for Foveros Die to Die interconnect and has been responsible for LINT, CDC, UPF delivery to the SOC team. He has also been involved in GPIO subsystem RTL development of discrete graphics SOCs and PCIE subsystem RTL integration to the SOC. Before joining Intel, Jayadev worked at Cypress Semiconductor Corporation and Broadcom, where he gained experience in Sr Elect Design Engr, DCD: WIFI Design India and Engineer Staff 1 roles, respectively. During his time at Broadcom, he got familiar with standard 802.11 a/b/n/ac/ax/p, worked on wireless 802.11 MAC low power design, and worked on PALLADIUM quick-turn emulation in the Wi-Fi chip DV team. Jayadev's educational background includes a Master of Technology (M.Tech.) in VLSI and CE from IIIT and a Bachelor of Engineering (B.E.) in Electronics and Communication from M.S. Ramaiah Institute of Technology. Jayadev's tech stack includes integration, and he has relevant experience of 7.70 years.