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Kashyap Shah
EDA Software Engineer at Intel Corp
About
Kashyap Shah is an experienced EDA (Electronic Design Automation) Software Engineer with over 6 years of professional experience. He has a strong understanding of Object-Oriented Programming C++ and Data Structures and Algorithms, and has worked extensively in Physical Design & Design Automation activities such as block level Timing Closure, Static Timing Analysis, and Signoff Flow development. Currently working at Intel as an EDA Software Engineer, Kashyap has also worked as a Principal Application Engineer at Cadence Design Systems, where he was responsible for Timing Signoff Methodology, Hierarchical STA, Context Analysis, and Boundary Model Generation. He has also worked as an Application Engineer, Sr. I at Synopsys. Kashyap holds a Master of Science (M.S.) degree in Electrical and Electronics Engineering from San Jose State University and a Bachelor's of Engineering degree in Electrical, Electronics and Communications Engineering from Gujarat Technological University. With a tech stack that includes Software Engineering, Kashyap has relevant experience of 8.19 years. He is open to networking and can be reached at kashyapshah91@gmail.com.
Education
• san jose state university
• gujarat technological university
Companies
• intel
• cadence design systems
• synopsys
• altera
Experience
9.1 Years
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Experience
Principal Application Engineer
cadence design systems | San Jose, California, United States
2021 - 2022
Skills
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Algorithms
Automation
C
C++
Data Structures
Design
eda
FPGA
Logic Synthesis
Perl
Physical Design
Place & Route
Software Engineer
Static Timing Analysis
TCL
Teamwork
Timing Closure
Verilog
VHDL
VLSI
Contact Details
Email (Verified)
kasXXXXXXXXXXXXXXXXXXomMobile Number
+18XXXXXXX79Education
san jose state university
Master of Science (M.S.)
2014 - 2015
gujarat technological university
Bachelor's of Engineering
2009 - 2013
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