About

Kaustubh Mundhada is a Lead Design Engineer at Analog Devices with over 6 years of experience in RTL design for novel and evolving communication systems, machine learning, neural networks, and processor architectures. He is currently working on architecture RTL design for high-speed RF signal chain and processor systems, with experience in ARM M4-based designs, AHB interconnects, matrices, and bridges. Kaustubh has designed dedicated matrix operation accelerators and floating-point operators, and has worked on the design of high-speed digital pre-distortion and signal chains using FIR filters. Kaustubh is experienced in power and timing-aware architecture and RTL implementation, as well as constraints for physical implementation flows. He has expertise in synthesis (Genus), PnR (Innovus), RTL power analysis (Joules), and gate power analysis (Tempus), as well as GLS flow and debug. Currently working at Essar, Kaustubh is responsible for the simulation of PLC automation systems for the paint industry. In his previous role as a summer intern at Samsung, he studied the complete architecture of the self-timed, high-speed SRAM compiler and carried out directed and UVM-based verification of different test-chip instances using FineSim. He also validated the trends in write margins with the variations in PVT parameters. As a student coordinator for the embedded team at the Kharagpur Robosoccer Students Group, Kaustubh designed and implemented a PID and fuzzy closed loop control for BLDC motor speed regulation on FPGA, improving performance by more than 30%. He also led the team to become the first Indian team to qualify in SSL even in RoboCup – 2016 in Germany, and the first Indian team to have won a Bronze medal at FIRA-15 in Miro-Sot event held in South Korea. Kaustubh holds a Bachelor of Technology (B.Tech.) in Electronics and Communications Engineering from the Indian Institute of Technology, Kharagpur. His tech stack includes ML, neural networks, test, and mobile.