About

Keertana Mutnuri is an experienced Front-End Design Engineer with over 8 years of experience in various aspects of digital and mixed signal IP/SoC design. She is currently working at Apple as a Front-end Design Engineer, where she is responsible for defining micro-architectural specifications for digital features and RTL design in System Verilog, running basic synthesis, STA, and other netlist checks to ensure implementation-friendly RTL, and assisting the Physical design team in IP timing closure. Prior to her current role, Keertana worked at Intel as a Senior IP Design Engineer, where she was responsible for microarchitecture and digital design, power management, and RTL to Physical Design quality. She also worked on silicon bring-up and debug to accelerate release to production and engaged in multiple task forces for critical customer issues across IPs, Firmware, Platform Validation, and Manufacturing teams. Keertana has received 30+ external customer and department recognitions for her work at Intel. Before joining Intel, Keertana worked at Microchip Technology Inc. as a Design Engineer, where she was responsible for RTL design of low-power deep-sleep controller and SoC integration of peripherals for 32-bit Microcontrollers, simulation and debug at IP & SOC level, ECO implementation and debug of Gate level sims (GLS), and post-silicon validation of low-power modes. Keertana holds a Master of Science degree in Electrical and Computer Engineering from Georgia Institute of Technology and a Bachelor of Engineering degree in Electronics and Communication from L.D College of Engineering. She attended Delhi Public School - Bopal, Ahmedabad, for her secondary education. Keertana's tech stack includes Frontend, test, and integration. With almost 10 years of relevant experience, Keertana has established herself as a skilled Front-End Design Engineer with expertise in microarchitecture, digital design, power management, and RTL to Physical Design quality.