About

Kiran Kumar Narayan is a skilled GPU Design Engineer at AMD with over 10 years of experience in Logic Design and DFT Logic Insertion. He holds a Masters Degree in Electronics and has a strong background in Integrated Circuits Technology. Currently, Kiran works as a Member of Technical Staff at AMD, where he specializes in GPU Accelerator Memory Sub-System Design. In this role, he is responsible for designing and implementing memory subsystem modules such as Cache, DMA, and DDR Model for Blaize GSP (GPU Accelerator) and SoC. Prior to joining AMD, Kiran worked as a Staff Hardware Engineer at Blaize (formerly Thinci), where he focused on designing memory subsystem modules for GPU Accelerator and SoC. He also served as a Member of Technical Staff at GlobalFoundries, where he designed Memory BIST IP and was responsible for DFT Insertion and verification for BIST IP and memory test-chip. Kiran's educational background includes a Masters Degree in Integrated Circuits Technology from the University of Hyderabad and a Bachelor's Degree in Electronics and Communications from JNTU. Kiran is a skilled Software Engineer, Tester, and Designer with a wealth of relevant experience. His expertise in Logic Design and DFT Logic Insertion make him a valuable asset to any team. Kiran is always looking for new challenges and opportunities to expand his skill set and contribute to innovative projects.