About

Krutik Shah is a seasoned professional with over 4 years of experience in the digital design flow, including micro-architecture design, RTL design, FPGA emulation, ASIC verification, embedded systems, VLSI design, and physical layout. As a Sr Application Engineer at Cadence Design Systems, he has demonstrated expertise in RTL design in VHDL, Verilog, and SystemVerilog, as well as languages like C, C++, Python, VHDL, Verilog, SystemVerilog, Bash, and PERL. Krutik has an excellent background knowledge of tools like Cadence Xcelium, JasperGold, Indago, and vManager, and a good understanding of System Verilog Assertions (SVA) and functional coverage. He is also well-versed in UVM verification methodology and has experience with UNIX/Linux. Krutik's past experiences include working as a Scientific Associate 3 at Brookhaven National Laboratory, where he designed a data acquisition system interfacing ASIC, ADC, and Kintex FPGA with JESD204B IP protocol. He also built an SV testbench for system-level end-to-end verification by writing random and directed test cases and simulated RTL design for verification, optimized timing, hardware resources, and algorithm for performance. At Juniper Networks, Krutik worked as a Software Engineer 2, where he gained expertise in computer networking fundamentals, JunOS operating system architecture, and features kernel design. He also developed features for JunOS command-line interface in C/C++ and configured networking devices developed by Juniper Networks for routing and switching. Krutik holds a Master of Science in Computer Engineering from New York University and a Bachelor of Technology in Electronics and Communications Engineering from Nirma University, Ahmedabad, Gujarat, India. He is proficient in test automation, Python, software engineering, and SDET. With his extensive experience and technical skills, Krutik is an asset to any organization that values innovation, quality, and excellence.