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Madhur Bhargava
Senior Manager, Questa Simulation R&D at Siemens EDA (Formerly Mentor Graphics)
About
Madhur Bhargava is a Lead Member Consulting Staff at Mentor Graphics, with over 13 years of experience in the software development industry. He specializes in the research and development of next-generation low power architecture, and has a solid background in software development with expertise in C/C++. Madhur has been proactively working in Questa PASim Team at Mentor Graphics for the past 6+ years, where he has been responsible for various features related to low power verification in Questa Simulation. He has designed and developed features like Power Aware Debug, UPF 2.0/2.1/3.0, Power States and composition, PA Static and Dynamic Checks. Additionally, he participates in IEEE 1801 UPF, actively contributing to the next revision of the IEEE standard. Madhur has authored several papers in the low power area and published online articles in the same field. He has also presented at various international forums and conferences, showcasing his expertise in C/C++, algorithms, data structures, design patterns, UPF, power-aware verification, low power verification methodologies, VHDL, and Verilog. Madhur completed his Bachelor of Engineering (BE) in Electronics and Communication from dtu in 2009. He also attended CRPF Public School. His tech stack includes C, software engineering, research science, and senior software engineering. Madhur's experience and expertise in low power architecture and software development make him an invaluable asset to any team.
Education Overview
• dtu delhi college of engineering
Companies Overview
• mentor graphics
• atrenta
• nsys design systems
• salora international ltd.
Experience Overview
15.1 Years
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