About

Manjunath Madakasira is an experienced ASIC Engineer with a strong background in Verilog, SystemVerilog, and Perl. He has worked on both the design and verification of complex modules in ASICs and has collaborated with peers from verification, physical design, and software development teams to drive closure of blocks with first pass success. Manjunath has domain expertise in networking and hardware acceleration and is skilled in creating microarchitecture, RTL implementation, logic synthesis, and timing analysis. Currently, Manjunath works as a Member of Technical Staff at Fungible, where he is working on the revolutionary Data Processing Unit (DPU). Prior to this, he worked as an ASIC Engineer III and II at Juniper Networks, where he designed and delivered bug-free designs such as chip-to-chip link, IO wrapper, and memory crossbar. He also performed verification at the module and full-chip level for two networking chips that provide over-subscription management and packet processing with queueing and buffering, respectively. Manjunath holds a Bachelor's degree in Electrical Engineering from IIT and a Master of Science in Computer Architecture from the University of Wisconsin-Madison. He also has experience in software engineering, testing, and integration, and has a total of 10.86 years of relevant experience in the field. With his strong technical skills and experience, Manjunath is a valuable asset to any team working on ASIC design and verification.